1. Technical Field
Various embodiments of the present invention relates to a semiconductor apparatuses and related methods. In particular, certain embodiments relate to a semiconductor apparatus and a test method thereof.
2. Related Art
Semiconductor apparatuses are usually verified through various tests prior to shipment as the final products. In general, a compression test is performed to reduce the test time and improve the test efficiency. The compression test can considerably reduce the test time because it is performed by compressing a plurality of data stored at the same level and detecting the level of the compressed data.
In order to increase the integration density, a 3-dimensional (3D) semiconductor apparatus that has a plurality of chips stacked in a single package has recently been developed. The 3D semiconductor apparatus has vertically stacked two or more chips to implement the maximum integration density in the same space.
Various methods are used to implement the 3D semiconductor apparatus. One of the methods stacks a plurality of chips with the same structure and connects the stacked chips by metal lines or wires so that they operate as a single semiconductor apparatus.
A through-silicon via (TSV) method has recently been used. In a TSV method, all of the stacked chips are electrically connected by a silicon via penetrating the stacked chips. Because chips are stacked and connected by a silicon via penetrating the stacked chips, a TSV-based semiconductor apparatus can effectively reduce the package area as compared to a semiconductor apparatus that has a plurality of chips connected by wire interconnections around the edges of the chips.
Various compression test circuits and methods have been proposed for single-chip packaged semiconductor apparatuses. However, few compression test circuits and methods have been proposed for multi-chip packaged 3D semiconductor apparatuses.